There are two basic types of transistors, namely Field Effect Transistors (FETs) and bipolar transistors. In general, current is conducted in FETs by charge carriers (e.g., electrons and holes) typically flowing through one type of semiconductor material, either n-type or p-type materials. In bipolar transistors, current passes in series through both n-type and p-type semiconductor materials.
Within the category of FETS, there are two basic types, namely the Metal Oxide Semiconductor (MOS) FET and the Junction FET (JFET). A primary difference between these two types of transistors is that the gate of the MOSFET has a layer of insulating material, typically referred to as gate oxide, between the gate and the other transistor electrodes. Consequently, channel current in a MOSFET is controlled by the application of electric fields across the channel to enhance and deplete the channel region, as operation requires. The gate of the JFET forms a PN junction with the other electrodes of the transistor, which can be reverse biased by the application of a predetermined gate voltage. Thus, the gate PN junction can be utilized to control the channel current by varying the extent of a depletion region to selectively dimension the current-carrying channel.
There are two different types of JFETs, an n-channel JFET and a p-channel JFET. In the n-channel JFET, carriers are electrons, and in the p-channel JFET carriers are holes. Additionally, the n-channel JFET includes an n-type channel and a p-type gate region, whereas the p-channel JFET includes a p-type channel and an n-type gate region.
JFETs are often employed in start-up circuits (e.g., for telecom and datacom equipment in central offices, PBXs, and servers) where a small current (mA) is supplied from a high (e.g., about 100 V) DC. One example of a schematic for a 110V start-up JFET for a telecom device is shown in FIG. 1. The JFET 100 includes a drain 110, a source 130, and a gate 170. The drain 110 is coupled to an input voltage (Vin) 120, the source 130 coupled to a supply voltage (Vdd) 140 and a bypass capacitor 150 via a voltage drop component 160, and the gate 170 is coupled to a gate control 180.
At the beginning of start-up, the gate control 180 provides a low-impedance path between gate 170 and source 130, giving Vgs near zero. This means that the JFET 100 is on and current will flow into the capacitor 150 and also to any load connected to the source terminal 140. In a typical start-up circuit, the load current is small and most of the current flows into the capacitor 150. The capacitor 150 charges, increasing vdd, which eventually reaches a desired operating value VddOp. At this point, the low-impedance path between gate 170 and source 130 is opened and a second low-impedance path is turned on between gate 170 and ground. These connections have the effect of reverse biasing the gate-source by VddOp volts. If VddOp is greater than the JFET pinch-off voltage, Vp, the JFET 100 will be turned off. If Vp exceeds VddOp, then additional voltage dropping components need to be added in series with the source to increase the magnitude of Vgs, for example diodes or a pnp bipolar transistor.
A JFET without specially designed protection structures will often experience leakage problem or instability at high voltage application. For example, at high voltage charges can spread from high voltage metal leads to low voltage areas along dielectric interfaces. When charges move onto specific regions, such as un-protected gate regions, they may cause surface inversion in certain scenarios. This may turn on a parasitic MOSFET, resulting in leakage. In other scenarios, depending on gate region doping profile, charges may cause instability in channel current.
Accordingly, what is needed in the art is a high-voltage JFET that experiences the benefits of the JFET design without suffering the drawbacks.